1. Field of the Invention
The present invention relates to an image processing technology, and it particularly relates to image processing method and apparatus for rendering three-dimensional objects to be displayed on a two-dimensional screen.
2. Description of the Related Art
In applications such as computer games and simulations which use many 3-D graphics, since the viewpoint from which a user views a 3-D object moves and the user moves 3-D objects, high-speed computer graphic (CG) processing is required. To be specific, every time an object or viewpoint moves, it is necessary to do high-speed rendering processing. In this processing the world coordinate of an object is transformed into a two-dimensional coordinate through perspective transformation. Based on this positional information and the texture features of the object surface such as colors and patterns, the color information is determined by pixel unit through rendering processing, which is then written in the frame buffer memory to be displayed on the screen.
In order to achieve higher speed rendering processing, there is a division processing method, in which a region to be rendered is divided into small tile regions and rendering is done in parallel per tile. With this method, called tile rendering, it is possible to do the majority of processing on the on-chip memory so the degree of dependence on external memory used as frame buffer is minimal. As a result, compared to existing graphic chips using 3-D pipeline, memory bandwidth can be narrower.
Also, there is a method, in which multiple graphic processors are driven in parallel. Each processor has VRAM and the rendering data processed by the respective graphic processors and Z-buffer, are synchronized and then output and externally consolidated into an image.
Since tile rendering differs greatly from the 3-D pipeline processing method, there is a compatibility problem with applications, and when the number of objects increases its efficiency is reduced because of sort processing. In the method where graphic processors are driven in parallel, parallelism is higher, but, since it is configured to use physically separate memory, the utilization of VRAM is poor and flexibility of operation is difficult. There is also a method in which a space is divided into evenly sized standard view volumes and image processing is done in parallel by standard view volume unit. But, in this method, since the space is divided without giving consideration to the shape and spatial position of a 3-D object, it is difficult to devise a flexible and optimal rendering stratagem, which reflects characteristics of each object.
Thus, it is clear that realizing compatibility and flexibility while at the same time improving memory efficiency and computing efficiency through increasing parallelism of rendering processing is a difficult challenge.